Computer Architecture

Pipelined RISC-V Processor

A five-stage pipelined RISC-V processor I designed and simulated by hand in Quartus schematics and Verilog.

PersonalDuration 3wContribution 100%2023-05 → 2023-06

Engineering Role

SystemsEmbedded

#Architecture #HDL #Personal #Verilog #Quartus #Developer #Hacker

Pipelined RISC-V Processor — Design schematic — Design schematic · EN

Overview

Final project for a computer architecture course. I built a five-stage (IF·ID·EX·MEM·WB) pipelined RISC-V processor with a 64-bit datapath from Quartus top-level schematics and Verilog modules — pipeline registers between stages, an opcode/funct-driven control unit, a forwarding unit that avoids data hazards, and the register file, memory, and ALU wired together — then verified add/sub/and/or·ld·sd·beq instruction sequences in logic simulation.

Highlights

IF/ID · ID/EX · EX/MEM · MEM/WB pipeline register design
Control unit + ALU control, forwarding unit for data hazards
Logic-simulation verification of R/I/S/SB-type instruction sequences

Timeline

2023-05 → 2023-06

Contribution: 100%

Collaboration: Personal

Tech Stack

</>Verilog · Quartus schematics · RISC-V

VerilogQuartus